PG VLSI Design Laboratory
PG VLSI
Design laboratory comprises of personal computers (18 Nos) and server system (2
Nos). Additionally 12 i7 systems were
purchased for working with Bluespec compiler. All the systems were installed
with Xilinx ISE design suite in windows and Cadence EDA tool in Linux
environment. MATLAB 7.14 is also installed along with Xilinx which contains HDL
Coder and additional toolboxes. Quartus 11 is also installed for implementing
the digital circuits in Altera DE1 image processing kit and DE3 – 260 Standard
board accompanied by the peripherals Multi touch LCD module and Mega pixel
Digital camera.
PG VLSI
Design Laboratory I course (for M.E. VLSI Design – Semester-I) comprises of
modelling the sequential and combinational circuits, writing test benches,
verifying the functionality of the design, interfacing the I/Os, implementing
the digital design in FPGA, applying the partial reconfiguration techniques
using the Universal FPGA Trainer kits (SPARTAN 3E). Designing the analog
circuits and verifying the functionality of the analog design using Cadence EDA
Virtuoso tool.
PG VLSI
Design Laboratory II Course (for M.E. VLSI Design – Semester-II) comprises of
designing VLSI architecture in Semicustom and full custom design methodologies
and running through Pre and Post layout simulation process and measuring the
performance of the design.
Semi-custom
design flow includes Specification, Design, synthesis and layout design (floorplanning,
place and route, power and clock distribution, clock tree synthesis, timing
analysis, power analysis, signal integrity, post-layout simulation and back
annotation, GDS-II generation) of digital building block. Full custom design
flow includes Specification, Schematic Design, simulation, layout generation,
Physical verification (LVS, DRC, RC extraction, post layout simulation, back
annotation, GDS-II generation) of analog building block.